[libre-riscv-dev] minimum viable ASIC

Luke Kenneth Casson Leighton lkcl at lkcl.net
Fri May 8 21:35:17 BST 2020

On Fri, May 8, 2020 at 8:08 PM Staf Verhaegen <staf at fibraservi.eu> wrote:
> Luke Kenneth Casson Leighton schreef op vr 08-05-2020 om 13:46 [+0100]:
> > On Fri, May 8, 2020 at 1:44 PM Yehowshua <yimmanuel3 at gatech.edu> wrote:
> > > I talked to Raptor and if Series A doesn’t pan out in August, Raptor is willing to foot 30k for PLL design in exchange for some equity.
> >
> > that's fantastic.  it would give us (and any other team)Foundry-independence.  normally the PLL is available as a StandardCell from a Foundry... but only under NDA.
> Be aware that PLL is an analog block meaning that if you let it design
> for a certain process from a certain foundry it will only work for that node and foundry.


> It is not portable like RTL code is unless specifically designed for that but
> analog designers typically don't know how to do that.

the professor at LIP6.fr knows what he is doing.

> Also in order to design the PLL you need NDA to access the PDK which likely
> also forbids making the final GDSII of your design public.

yes, have to be realistic about that.

thanks Staf.


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