[libre-riscv-dev] PowerISA 3.1 (Power10) spec released

Luke Kenneth Casson Leighton lkcl at lkcl.net
Tue May 12 09:33:52 BST 2020

On Tue, May 12, 2020 at 9:22 AM Lauri Kasanen <cand at gmx.com> wrote:

> It's just a name though, even the doc says you can run Linux on the
> lower levels.

yes... you can.... however note the phrase "Linux Compliancy".  this
means that they have plans for actual Compliance Test Suites.  this in
turn will mean that

one option therefore is to have a software-driven emulator mode for
SIMD.  this would be our responsibility to write and maintain.

> It's fine for libresoc to be at the int+fp level, and
> include optional features from above that are useful. I just wanted to
> point out the BE/LE requirement as it surprised me at least.

yeh - in the West it is just not known that the majority of S.E.Asia
industry runs on BE hardware that is often 40 years old (VME Bus).

> BE for instructions is not full BE, as data changes too.

i recall (and could be wrong about) seeing that there's different
bits, one covering instructions, one covering data.  would need to
read them more closely.  are you saying that the BE-for-instructions
bit will flip *data* order as well?

 See Section 1.10 of Book I and its first two subsections. Also see
the description
 of the ILE field of the LPCR in Section 2.2 of Book III and the
description of the
 LE bit of the MSR in Section 4.2.1 of Book III.


Interrupt Little-Endian (ILE)
The contents of the ILE bit are copied into
MSRLE by interrupts that set MSRHV to 0 (see


63 Little-Endian Mode (LE)
0 The thread is in Big-Endian mode.
1 The thread is in Little-Endian mode.

if we are to flip the instruction stream to BE mode (to support the
SVP/C/VBLOCK capability) we definitely don't want data to flip as

bottom line: if there *isn't* a separate bit for instructions-BE/LE
and data-BE/LE, we definitely need one.


More information about the libre-riscv-dev mailing list