[libre-riscv-dev] PowerISA 3.1 (Power10) spec released
cand at gmx.com
Tue May 12 09:23:14 BST 2020
On Tue, 12 May 2020 08:50:09 +0100
Luke Kenneth Casson Leighton <lkcl at lkcl.net> wrote:
> On Tue, May 12, 2020 at 7:00 AM Lauri Kasanen <cand at gmx.com> wrote:
> > level. However the Linux level requires SIMD.
> this is more serious. the implementation burden of POWER SIMD
> compliance is absolutely massive. a quick count from figure 91 i
> estimate 600 instructions dedicated to INT and FP SIMD.
> the scalar instruction set is much more manageable: there's 378
> opcodes from microwatt CSV files, then there's 20 FP LD/ST, and
> estimated 70 or so FP arithmetic and 8 or so status registers.
It's just a name though, even the doc says you can run Linux on the
lower levels. It's fine for libresoc to be at the int+fp level, and
include optional features from above that are useful. I just wanted to
point out the BE/LE requirement as it surprised me at least.
BE for instructions is not full BE, as data changes too.
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