[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Fri May 8 17:48:11 BST 2020


--- Comment #8 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #4)
> Created attachment 52 [details]
> scoreboard mechanics image
> michael can you drop this onto the wiki scoreboard page

thank you.  meeting still not happened yet, waiting for a call, did
a quick section and also added the corresponding write diagram

so just to emphasise, michael: for ALUInitialData it will need:

+class ALUInitialData(IntegerData):
+    def __init__(self, pspec):
+        super().__init__(pspec)
+        self.a = Signal(64, reset_less=True)
+        self.b = Signal(64, reset_less=True)

plus XER carry-in as an input operand and also the opcode itself.
although... that's going to be in ctx, as opkls?  hmm... see separate

and a *separate* output class (not the same as ALUInitialData)
will be needed with:

* output result (RT)
* CA CA32
* CR0
* SO OV OV32

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