[libre-riscv-dev] daily kan-ban update 08mar2020

[Luke Kenneth Casson Leighton]

On Fri, May 8, 2020 at 2:52 PM Yehowshua <yimmanuel3 at gatech.edu> wrote:
>
> OK. Lemme have a go at this.

bugreport.  link to the interfaces page
https://libre-soc.org/180nm_Oct2020/interfaces/

> So I know we need LPC. Discussions with Raptor would have us use LPC to grab the boot loader externally I believe.

it's far more trivial even than that.  you literally set the Program
Counter to an address that is mapped to the LPC's memory-mapped
address.  that's it.  the Instruction Q fetch makes a request for an
instruction, that request goes over wishbone, wishbone directs it to
the LPC's memory-mapped peripheral, the LPC translates it into a "LPC
style memory request", the data comes back at that address.

it's so ridiculously not complicated it's actually "difficult to
understand why it's not more complicated".


> Here is some sample code for having the LCP sit as a wishbone slave.

ahh goooood.  perfect!

> Is Rudi on the mailing list yet?

no and i'm going to recommend he not be distracted by it.  define the
task, give him the task, and trust him to do it.  he's done massive
ASICs for some really large companies, multi-million-dollar work,
gigabit SERDES and last time i talked to him he was looking at doing a
USD $20m ASIC.

> https://gitlab.raptorengineering.com/raptor-engineering-public/lpc-spi-bridge-fpga/blob/master/lpc_interface.v#L1162 <https://gitlab.raptorengineering.com/raptor-engineering-public/lpc-spi-bridge-fpga/blob/master/lpc_interface.v#L1162>