[libre-riscv-dev] [Bug 296] idea: cyclic buffer between FUs and register file

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=296

Jacob Lifshay <programmerjake at gmail.com> changed:

           What    |Removed                     |Added
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                 CC|                            |programmerjake at gmail.com

--- Comment #2 from Jacob Lifshay <programmerjake at gmail.com> ---
Seems like a good idea, however out-of-order (and in-order) processors depend
on single-cycle forwarding between the results of one operation and the input
of the next for most of their performance, the forwarding network would need to
keep that property (haven't fully thought through if this idea keeps that
property).

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