[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=305

--- Comment #48 from Michael Nolan <mtnolan2640 at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #47)
> ok let's put the forms side-by-side, from fields.txt
> 
> #1.6.4 D-FORM
>    | OPCD |    RT      |   RA|   D        |
> 
> # V3.0B 1.6.6 DX-FORM
>    | OPCD|  RT|   d1|   d0|   XO|d2
> 
> # 1.6.16 XO-FORM
>    | OPCD |  RT|   RA|   RB  |OE |   XO |Rc  |
> 
> 
> and the shift ones are:
> 
> # 1.6.18 M-FORM
>    | OPCD |  RS |   RA |   RB |   MB |   ME |Rc|
> 
> # 1.6.19 MD-FORM
>    | OPCD |  RS |   RA |   sh |   mb |XO|sh|Rc|
> 
> # 1.6.7 X-FORM
>    | OPCD |       RT      |    RA       |     ///     |   XO |  / |
> 
> 
> so... well... i'm not actually seeing any 3-operand-input forms, there.
> they're all 2-operand or 1-operand-plus-immediate.
> 
> note: 3-operand *input* not 3-operand *total including output operand*.
> 
> so i'm now wondering what on earth is going on, because we shouldn't need
> to be reading reg3 at all.
> 
> any clues?

We only need two register operands and an immediate for all ALU instructions.
The only ones with 3 register operands are store indexed instructions

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