[libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=353

--- Comment #4 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Cole Poirier from comment #3)
> (In reply to Luke Kenneth Casson Leighton from comment #2)
> > (In reply to Cole Poirier from comment #1)
> > > if this proof is needed before then for the virtual_port tests,
> > 
> > it's not.  i have a preliminary virtual_port test running, yesterday.
> 
> Saw your 'proof-of-concept' test case yesterday, was helpful for
> understanding the functionality of the module further. Unfortunately, I
> think this test is now failing with the following error:
> 
> ```
> Traceback (most recent call last):
>   File "virtual_port.py", line 203, in <module>
>     test_regfile()
>   File "virtual_port.py", line 200, in test_regfile
>     vcd_name='test_regfile_array.vcd')
>   File "/home/colepoirier/src/nmigen/nmigen/compat/sim/__init__.py", line
> 22, in run_simulation
>     fragment.domains += ClockDomain("sync")
> AttributeError: 'VirtualRegPort' object has no attribute 'domains'
> ```

then you know what to do there: inspect line 22 of that file, and check
it against the latest version of nmigen, online.  have a look:
https://github.com/nmigen/nmigen/blob/master/nmigen/compat/sim/__init__.py


    if not isinstance(generators, dict):
        generators = {"sync": generators}
        if "sync" not in fragment.domains:
            fragment.add_domains(ClockDomain("sync"))


does that match with what you have?

> Indeed, it seems to be a very productive strategy. Looking forward to
> working with you on the proof today. Just reviewing my notes now, should
> have some code for some of the basic assumptions committed in the next hour.

cool.

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