[libre-riscv-dev] daily status update 05may2020

Michael Nolan mtnolan2640 at gmail.com
Tue May 5 23:04:09 BST 2020

On 5/5/20 3:11 PM, Tobias Platen wrote:
> Today I was mostly reading documentation for the add[o][.], subf[o][.], adde*, subfe*, addze*, neg*, mullw*, divw* instructions that I will implement tomorrow in the simulator.

Which simulator are we using now? There's internalop_sim.py and the 
autogenerated one in decoder/isa.


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