[libre-riscv-dev] daily status update 05may2020

[Luke Kenneth Casson Leighton]

On Tuesday, May 5, 2020, Michael Nolan <mtnolan2640 at gmail.com> wrote:

> On 5/5/20 3:11 PM, Tobias Platen wrote:
>
>> Today I was mostly reading documentation for the add[o][.], subf[o][.],
>> adde*, subfe*, addze*, neg*, mullw*, divw* instructions that I will
>> implement tomorrow in the simulator.
>>
>
> Which simulator are we using now? There's internalop_sim.py and the
> autogenerated one in decoder/isa.


autogenerated.  good catch michael.  no need to implement code that already
exists.

unit tests need to be written for them however, to confirm that they work.
that funnily enough is more work as you have to test corner cases esp. on
carryin and out.

l.



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