[libre-riscv-dev] [Bug 304] Define minimum viable interface set for 180nm ASIC

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=304

Yehowshua <yimmanuel3 at gatech.edu> changed:

           What    |Removed                     |Added
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                   |/2020-May/006374.html       |

--- Comment #2 from Yehowshua <yimmanuel3 at gatech.edu> ---
Relevant Links:

http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-May/006374.html
http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-May/006372.html
https://libre-soc.org/shakti/m_class/pinouts/
https://gitlab.raptorengineering.com/raptor-engineering-public/lpc-spi-bridge-fpga/tree/master

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