[libre-riscv-dev] [Bug 351] create a "block" (mass) regfile port (read and write) onto an array-based regfile

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=351

Cole Poirier <colepoirier at gmail.com> changed:

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                 CC|                            |colepoirier at gmail.com

--- Comment #4 from Cole Poirier <colepoirier at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #2)
> https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=HEAD
> 
> saw this.

Thanks! I'm trying to get something down, so I don't freeze because there are
multiple things I don't understand.

> 
> i think... actually... the list  of ports in the constructor, have to be
> done manually, then those wired via a mux to the "real" ports
> 
> so a for loop adds RecordObjects
> 
> ren=1, data=bitwidth/nregs
> 
> then appends an *extra* on
> ren=nregs, data=bitwidth

Pushed a commit with this change, not sure if it's exactly right yet.

> 
> then in the constructor:
> 
> * test port[-1].ren == 0
> 
> * if zero then for all ports 0 to nregs, connect *internal* port to external
> port
> 
> * else put bitwidth/nregs bits of port[-1].data onto port[loopindex].data
> and also do same with enable bits.

Can you help me undestand how I should set the interal and external ports up in
the __init__() function? I'm lost here as to how these should be represented in
code.

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