[libre-riscv-dev] [Bug 155] a PLL is needed for the SoC

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=155

--- Comment #13 from Dimitri Galayko <dimitri.galayko at lip6.fr> ---
Dear all, I'm following the discussion by mail with Luke. There is a need to
create a "open-source" and generic PLL with the following specifications: 

Technology: TSMC 180 nm
Input: 24 MHz XTAL
Output Frequency: ~300 MHz (~x12), with fractional intermediate frequencies x2,
x3, x4, x5, x6. A double of the frequency needs to be generated, in order to
have a 300 MHz well-balanced 1 and 0 phases. 

Goal : to include to October tape-out
Power: TBD -- the whole chip is expected to consume 3 watts 
Jitter specifications : TBD 

I believe that an all-digital PLL can be a good first approach, if the design
needs to be “generic”. The most critical and difficult block is the digitally
controlled oscillator, which defines greatly the performances of the whole. 

We have a multiple experience of design of all-digital PLLs, whose basic blocks
(mainly DCO and phase detector) have been inspired from the work (done in 65 nm
CMOS)
**Tierno, Jose A., Alexander V. Rylyakov, and Daniel J. Friedman. "A wide power
supply range, wide tuning range, all static CMOS all digital PLL in 65 nm SOI."
IEEE Journal of Solid-State Circuits 43.1 (2008): 42-51. **
A detailed report on what have been done in my team is available in the PhD
report (in english, available on the web)
**Shan, Chuan. Générateur distribué d'horloge pour puces globalement et
localement synchrones de grande taille. Diss. Paris 6, 2014.** 

The advantage of this approach is a compatibility with the digital design flow,
all blocks belong to the digital electronics (even if some of them require a
custom sizing). I believe that this is well suitable for the goal of a
“generic” design flow. After that, it is possible that the performances will
not be satisfactory in 180 nm (mainly the power consumption), I have some idea
about possible alternative. 

My first simulations in a 180 nm technology (not TSMC, but equivalent) shows
that a 8 bits DCO may ensure a 600 MHz output frequency for all corners with a
resolution able to provide a reasonably good jitter performance, with the power
consumption of ~5mW.  

So, regarding the specifications, the most important point determining the
overall architecture is : 
-- Jitter 
-- power consumption. 

Is there any idea about what is expected for these two specifications ?

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