[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=305

--- Comment #18 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Michael Nolan from comment #16)

> Summary Overflow is "sticky". Once one instruction sets the overflow bit,
> summary overflow gets set until it's cleared by a mtspr instruction.
> Effectively for each instruction it's (so = so | ov). That's why it's
> included in the input stage.

ohhh. yep.  got it now.  can you drop a comment into the data structure to that
effect? the idea being that "why is this here" should be answered (or, a
reminder of the answer)

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