[libre-riscv-dev] Needed Subset of POWER

Luke Kenneth Casson Leighton lkcl at lkcl.net
Sun May 3 00:34:52 BST 2020

On Saturday, May 2, 2020, Yehowshua <yimmanuel3 at gatech.edu> wrote:

> Hello all,
>         I’m reading through the Power ISA manual. What subset of POWER are
> we doing for the first single core revision?

not vector, that's for sure.  it's half the 1200 pages.  we do however need
to come up with an interoperability  solution for not having them.

> What is the minimal subset of POWER that we can get away with for an
> operational Linux kernel?

a GPIO subsystem, interrupts, MMU (RADIX), integer, branch, LD/ST,
hypervisor, SPRs, and a little bit more.

FP not needed.  see power-gem5 simulator branch.  am on phone. links in
bugzilla somewhere.  search "gem5".

> There are lots and lots of features such as:
> ```
> Decimal Floating-Point Support Operations: Add imme- diate forms of DFP
> Test Significance instructions.

not that.  not transactions, either

> ```
> Do we have to implement all these “icing” instructions eventually to be
> POWER certified?

i hear this is still being decided.

i do not speak for the Foundation, my understanding is, it will probably be
*guided* by what microwatt can reasonably implement.

asking IBM is unfortunately not quite... how can i put it.... because they
have incrementally got to such a staggering level of functionality over so
many years i'm not quite certain that they are truly aware how high the bar
has become.

microwatt and chiselwatt development will help them to appreciate that.


crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

More information about the libre-riscv-dev mailing list