[libre-riscv-dev] [Bug 333] investigate why CR pipeline code took 100% CPU and locked up generating ILANG

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=333

--- Comment #28 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
ehhhm... i don't actually think main_stage.py needs *any* of these.

* registers are identified and passed in according to DecodeCRIn/Out
  in combination with regspecs

* fn_unit might be a good idea to leave in

* insn_type is pretty much literally the only thing that's actually
  used, isn't it?

there's nothing in CR main_stage.py which is different for 32/64 bit, is there?
read_cr_whole and write_cr_whole might be useful information if we decide
to do MUXing, but that would be back at the CRCompUnit

do we need input_cr or output_cr - i mean in main_stage.py?  i don't
think we do.


class CompCROpSubset(Record):
    def __init__(self, name=None):
        layout = (('insn_type', InternalOp),
                  ('fn_unit', Function),
                  ('input_cr', CRInSel),
                  ('output_cr', CROutSel),
                  ('read_cr_whole', 1),
                  ('write_cr_whole', 1),
                  ('is_32bit', 1),
                  )

-- 
You are receiving this mail because:
You are on the CC list for the bug.