[libre-riscv-dev] [Bug 333] investigate why CR pipeline code took 100% CPU and locked up generating ILANG

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=333

--- Comment #29 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
ah, just realised: the convention for outgoing regs is to use Data()
main_stage.py (or output_stage.py) then sets "ok" to indicate that
it has been modified.  will do that now.

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