[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=305

--- Comment #12 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #11)
> (In reply to Michael Nolan from comment #10)
> > Does it make sense to have the ALU inputs a and b be PartitionedSignals?
> 
> later.  not right now.  if we have time we convert them to
> PartitionedSignals.

i know :)  we did all that work and we need to focus first on a
scalar version.  it means not needing to fuss about parallel-masked
decisions and so on, which i am expecting shouuuld make development
time faster.

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