[libre-riscv-dev] [Bug 350] LDSTCompUnit also needs to support zeroing on RA

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=350

--- Comment #2 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #1)
> added, untested, however may have a block when both zero and immediate set.

it's fine.  unit test modified as follows:

+    rd = 0b00
+    if not imm_ok:
+        rd |= 0b10
+    if not zero_a:
+        rd |= 0b01
+
+    if rd:
+        yield dut.rd.go.eq(rd)
+        yield from wait_for(dut.rd.rel)
+        yield dut.rd.go.eq(0)

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