[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=305

--- Comment #14 from Michael Nolan <mtnolan2640 at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #13)

> with "carry_in" being *generated* by ALUInputStage, ALUInputData should
> *not* have "carry_in" as a field.

We still need a carry_in from XER for things like add with carry. 

> the reason is because it will never be set by the *user* of this stage,
> and consequently a dangling wire will end up being created.
> -----
> 
> what's "so" intended for?

Summary Overflow.

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