[libre-riscv-dev] [Bug 318] fix LDSTCompUnit

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=318

--- Comment #3 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
the "ultimate" success test of this is for experiment/score6600_multi.py
to not go permanently into "busy" mode.

the videos show how LDSTCompUnit is *supposed* to work... but doesn't
quite.

the issue on the current commit is that the address latching is not
occurring - not being transferred through correctly to mem_w_data -
for ST operations.

i *think* it is working fine on LD operations.

you can see in the gtkwave timing diagram that:

* cycle @ 50ns mem_w_en (and so mem_w_data) change
* however cycle @ 40ns *should* have set mem_w_addr to 0x6

this *actually* occurs 4 cycles later for the *second* ST operation!

if you then look at alu_o (further up), you can see it is:

* 0x0002 @ 20ns
* 0x0006 @ 30ns (the required, correct value)
* however ad__rel - the signal that says "address is valid"
  was *one cycle early*

(ad__rel in gtkwave is the name for the object ad.rel, and there is
a "convenience" variable in the python code ad_rel_o which points
to self.ad.rel)

it's nearly there.

notes:

* every req signal (rd.req[0], rd.req[1], rd.req[2], wr.req[0],
  wr.req[1], ad.req and st.req) has a corresponding "go" signal
  (rd.go[0] etc.)

  these are from the data structure created on-the-fly by
  "go_record"

* outgoing request ("req") signals may be held ASSERTed indefinitely until
  such time as their associated "go" signal is ASSERTed for one cycle

* on assertion of the corresponding "go" signal, the associated "req"
  signal **MUST** be de-asserted

this is basically wishbone etc. etc. etc. standard ready_o / valid_i
signalling conventions

in TestLDSTCompUnit, you can see the following line:

        m.d.comb += self.ad.go.eq(self.ad.rel) # link addr-go direct to rel

this is done deliberately because otherwise it becomes necessary to write
a split pair of co-routines in the unit test:

* one that watches ad.rel and sets ad.go for one cycle
* one that watches wr.rel[1] and sets wr.go[1] for one cycle

strictly speaking *all* {sig}.go signals could be made equal to all {sig}.rel
signals, combinatorially, and the code should function perfectly correctly.

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