[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=336

--- Comment #37 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Cesar Strauss from comment #36)
> (In reply to Luke Kenneth Casson Leighton from comment #35)
> > it will be fascinating to compare against the formal proof
> 
> I saw src/soc/fu/compunits/formal/proof_fu.py. Very interesting.

it is also very "clean".

> How about a formal proof of the ALU interface?

the interaction with it will be needed, yes, because of the signalling
ready/valid.

in particular the ALU may *not* necessarily be ready to proceed at the time
operands are available.

> Also, maybe DummyALU could be truly dummy (doesn't drive its signals), and
> let Assume drive them, in the CompUnit formal proof.

i have no idea.  we do need some way to check that data actually gets passed
through.

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