[libre-riscv-dev] [Bug 316] bperm TODO

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=316

Michael Nolan <mtnolan2640 at gmail.com> changed:

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--- Comment #18 from Michael Nolan <mtnolan2640 at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #17)
> (In reply to Cole Poirier from comment #16)

> 
> btw notice in cr/main_stage.py, michael also does the same "indexing" trick
> :)
> in particular notice what he does with the name argument:
> 
>    cr_out_arr = Array([Signal(name=f"cr_out_{i}") for i in range(32)])
> 
> if you try that out you will end up with actual properly-named Signals rather
> than "stuff that's randomly named $1, $2, $3.... $64".

ROFL, I got the idea of using Arrays from your conversations yesterday.

> 
> 
> > Now I am going to go over Robert Baruch's
> > nmigen tutorials and search out resources on writing unit tests, and formal
> > proofs for hardware. Then I will attempt to write an appropriate unit test
> > for this class.
> 
> great.  formal proofs are... odd.  i can barely get my head round them.

I'd be happy to help with formal proofs when you're ready.

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