[libre-riscv-dev] [Bug 308] New: POWER variable-length encoding scheme needed

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Wed May 13 10:37:52 BST 2020


            Bug ID: 308
           Summary: POWER variable-length encoding scheme needed
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: PC
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Specification
          Assignee: lkcl at lkcl.net
          Reporter: lkcl at lkcl.net
                CC: libre-riscv-dev at lists.libre-riscv.org
   NLnet milestone: ---

instruction stream order needs to be sorted out so that the proposed
Compressed/48/64/VBLOCK encoding will fit.  currently, LE on POWER
is wholly unsuited to variable-length ISA encoding due to the opcode
being at the wrong end of a sequential instruction byte stream



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