[libre-riscv-dev] daily kan-ban update 22may2020

Cesar Strauss cestrauss at gmail.com
Sat May 23 11:24:15 BST 2020

On 05/22/2020 23:41, Luke Kenneth Casson Leighton wrote:
> On Saturday, May 23, 2020, Cesar Strauss <cestrauss at gmail.com> wrote:
>> My motivation to participate in Libre-SOC:
>> A libre, supported, fully documented SoC, free of proprietary drivers,
>> firmware and bootloaders, that I can trust to use in my workstation,
>> server and as building blocks of scientific instruments.
> very cool.
> and even in FPGA, one that had good number crunching capability might be
> useful, i assume.

If you mean a libre FPGA, I am all for it.

A libre, supported, fully documented FPGA, with open architecture and
bitstream format.

If some people (hint!) were to start a libre-FPGA project, it would be
absolutely wonderful.

Independent of having a number crunching capability or not.

For synthesis, placing and routing, we do have libre tools. But, to
actually program the Configurable Logic Blocks (CLB), the routing switch
matrices, etc., inside the FPGA, we are forced to either use the
proprietary tools, or use libre tools based on a reverse engineered
bitstream format. It's a complete lock-in.

The community did produce a completely libre flow, from HDL to
bitstream, for Lattice chips. But the bitstream format is still
proprietary, and had to be reverse engineered. It is not assured that we
always will be able to do so, as new families are introduced. It is a
waste of effort, and features will be lacking.

I think there are experimental FPGAs developed in academia, but not
reaching commercial availability.



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