[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=305

--- Comment #61 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #60)

> i wonder... i wonder if, rather than mess up the input stage *and* the
> main stage, which involves two 64-bit MUXes, if it would not be better
> to swap is_positive and is_negative in the *output* stage?
> 
> this would only be QTY 2 single-bit MUXes

i'll give this a shot, see what happens.

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