[libre-riscv-dev] [Bug 314] Create POWER9 Condition Register pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=314

--- Comment #18 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
i'm so excited, i'm so happy, i added an instruction (isel).

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