[libre-riscv-dev] [Bug 314] Create POWER9 Condition Register pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=314

--- Comment #17 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/cr/pipe_data.py;h=2894144fd814444a7bdb75ae6c695af8519ae084;hb=HEAD

can add b to CRInputData.

https://libre-soc.org/openpower/isa/fixedtrap/

what on earth isel is doing in the trap instruction group is beyond me.  could
be i just put the pseudocode in the wrong file

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