[libre-riscv-dev] minimum viable ASIC

[Luke Kenneth Casson Leighton]

On Friday, May 8, 2020, Staf Verhaegen <staf at fibraservi.eu> wrote:

>
> Why only 24MHz without PLL ? You should have problems getting external
> clock frequencies up to 100MHz without a problem inside a chip.
>

really? great!  and that's driven from an external 100mhz clock?  it seems
a little high, i guess i am used to SoCs which all run from a 24mhz XTAL.

l.




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