Luke Kenneth Casson Leighton schreef op vr 08-05-2020 om 10:50 [+0100]: > > * a PLL (this is quite a lot however it turns the ASIC from a 24mhz > design into a 300mhz design) Why only 24MHz without PLL ? You should have problems getting external clock frequencies up to 100MHz without a problem inside a chip.