[libre-riscv-dev] minimum viable ASIC

Staf Verhaegen staf at fibraservi.eu
Fri May 8 11:29:45 BST 2020

Luke Kenneth Casson Leighton schreef op vr 08-05-2020 om 10:50 [+0100]:
> * a PLL (this is quite a lot however it turns the ASIC from a 24mhz
> design into a 300mhz design)

Why only 24MHz without PLL ? You should have problems getting external
clock frequencies up to 100MHz without a problem inside a chip.

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