[libre-riscv-dev] minimum viable ASIC
staf at fibraservi.eu
Fri May 8 12:10:52 BST 2020
Luke Kenneth Casson Leighton schreef op vr 08-05-2020 om 11:42 [+0100]:
> On Friday, May 8, 2020, Staf Verhaegen <staf at fibraservi.eu> wrote:
> > Why only 24MHz without PLL ? You should have problems getting externalclock frequencies up to 100MHz without a problem inside a chip.
> really? great! and that's driven from an external 100mhz clock? it seemsa little high, i guess i am used to SoCs which all run from a 24mhz XTAL.
There exist clock generator chips, some of them even programmable over a serial bus interface. In the retro world amiga 75MHz accelerator cards or above are not unheard of.
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