[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=325

--- Comment #1 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
* twi TO,RA,SI
* tw TO,RA,RB

    a <- EXTS((RA)[32:63])
    b <- EXTS((RB)[32:63])
    if (a < b) & TO[0] then TRAP
    if (a > b) & TO[1] then TRAP
    if (a = b) & TO[2] then TRAP
    if (a <u b) & TO[3] then TRAP
    if (a >u b) & TO[4] then TRAP

Special Registers Altered:

    None

so, here, inputs are:

* RA
* RB (or imm)
* MSR (where does this come from?)

logic is identical to CMP


outputs are:

* NIA
* SRR1 (SPR)

see
https://github.com/antonblanchard/microwatt/blob/master/execute1.vhdl

irq_nia <= (to_unsigned(16#700#, 64));
srr1 <= msr_copy(ctrl.msr);
-- set bit 46 to say trap occurred
srr1(63 - 46) <= '1';


this one although it smells like a Branch it actually seems to smell more like
a MicroCoded double op, a combination of OP_CMP and OP_BR.

i am reluctant to suggest we do microcoding for this design right now

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