[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Mon May 11 17:13:53 BST 2020


--- Comment #42 from Michael Nolan <mtnolan2640 at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #40)
> hmmm hmmm hang on hang on - this is removing the order.  if there's 3 regs,
> then 3 regs are needed.
> what's needed is like this:
> <snip>...</snip> 
>     yield alu.p.data_i.a.eq(input[0][0]) # RA
>     yield alu.p.data_i.b.eq(input[1][0]) # RB
>     yield alu.p.data_i.c.eq(input[2][0]) # RC
I went through the tables and double checked, the *only* ALU instructions that
have 3 inputs are 2 registers and an immediate. It does not *need* 3 register

However, some piece of hardware needs to order the inputs, I guess the trade
off is whether to do it in the alu or somewhere else.

You are receiving this mail because:
You are on the CC list for the bug.

More information about the libre-riscv-dev mailing list