[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Mon May 11 17:13:04 BST 2020


--- Comment #41 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
ok - *sigh* - we _could_ define it this way however if you look in
the decode1/2.vhdl you'll see that anton's team defined RS == RC.


output reg is defined as RA and RT (yes we need a 2nd one)

in this way i believe RB *always* ends up as "the register that
can be replaced by an immediate at the input side"


you see what i mean?

so it's because reg positions are lost that RA suddenly receives reg data
that was supposed to be in RB

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