[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=336

--- Comment #16 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Cesar Strauss from comment #15)
> Found this:
> 
> https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/experiment/
> compalu_multi.py;h=75df2153517ecd733cd5270776e88d76b8df5d06;hb=HEAD#l213
> 
>     name = "data_r%d" % i
>     data_r = Signal(self.cu._get_srcwid(i), name=name, reset_less=True)
>     latchregister(m, self.get_out(i), data_r, req_l.q[i], name)
> 
> We are giving the same name for two things, the output signal of the
> latchregister, and its internal DFF (given by the function parameter).
> nMigen will append "$1" to one of them, but which?

wonderful, isn't it?

> Can we go and choose a name, given to its internal DFF, different from its
> output, in this and similar cases?

sure.  i'd suggest doing this:
     latchregister(m, self.get_out(i), data_r, req_l.q[i], name)
-->
     latchregister(m, self.get_out(i), data_r, req_l.q[i], name+"_l")

> 
> Also:
> 
> https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/experiment/
> compalu_multi.py;h=75df2153517ecd733cd5270776e88d76b8df5d06;hb=HEAD#l208
> 
>     latchregister(m, self.oper_i, oper_r, self.issue_i, "oper_r")

sure - feel free to call it "oper_l" instead

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