[libre-riscv-dev] [Bug 316] New: bperm TODO

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=316

            Bug ID: 316
           Summary: bperm TODO
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: PC
                OS: Linux
            Status: CONFIRMED
          Severity: normal
          Priority: ---
         Component: Source Code
          Assignee: lkcl at lkcl.net
          Reporter: colepoirier at gmail.com
                CC: libre-riscv-dev at lists.libre-riscv.org
   NLnet milestone: ---

Assigned to me by Luke as a first nmigen excercise.

pseudo-code here:
perm <- [0] * 8
for i = 0 to 7
index <- (RS)[8*i:8*i+7]
if index < 64 then
perm[i] <- (RB)[index]
else
perm[i] <- 0
RA <- [0]*56 || perm[0:7]

I am to see if I can write the above in nmigen. Below is the simulation
version (translated from the above pseudo-code), it may be easier to
understand:

@inject()
def op_bpermd(self, RS, RB):
perm = concat(0, repeat=8)
for i in range(0, 7 + 1):
index = RS[8 * i:8 * i + 7 + 1]
if lt(index, 64):
perm[i] = RB[index]
else:
perm[i] = 0
RA = concat(concat(0, repeat=56), perm[0:8])

notes:

* repeat=8 you use Repl
* concat you use Cat
* index you will have to actually store that in a temporary Signal (8
bits in length)

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