[libre-riscv-dev] [Bug 348] New: POWER9 SPR pipeline needed

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=348

            Bug ID: 348
           Summary: POWER9 SPR pipeline needed
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: PC
                OS: Mac OS
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Source Code
          Assignee: lkcl at lkcl.net
          Reporter: lkcl at lkcl.net
                CC: libre-riscv-dev at lists.libre-riscv.org
   NLnet milestone: ---

OP_MTSPR, OP_MFSPR operations to be added to an SPR pipeline.
with some of the SPRs being in a separate regfile (XER, LR, CTR, SRR1, SRR2)
this pipeline is slightly more involved than it seems.   it also requires
quite a lot of regfile ports.

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