[libre-riscv-dev] [Bug 323] create POWER9 MUL pipeline

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Tue May 19 13:24:58 BST 2020


--- Comment #1 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
there are actually two different types of MUL here.

* VA Form - 3 int in, no carry/overflow
* X Form - usual style just like ALU/Logical

my feelings are mixed as that is a lot of ports if they are combined. still,
actuslly, after some thought it is the same (after combining) port allocation
as Shift.

# Multiply-Add High Doubleword VA-Form


* maddhd RT,RA.RB,RC

    prod[0:127] <- (RA) * (RB)
    sum[0:127] <- prod + EXTS(RC)
    RT <- sum[0:63]

Special Registers Altered:


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