[libre-riscv-dev] [Bug 323] create POWER9 MUL pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=323

--- Comment #1 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
there are actually two different types of MUL here.

* VA Form - 3 int in, no carry/overflow
* X Form - usual style just like ALU/Logical

my feelings are mixed as that is a lot of ports if they are combined. still,
actuslly, after some thought it is the same (after combining) port allocation
as Shift.


# Multiply-Add High Doubleword VA-Form

VA-Form

* maddhd RT,RA.RB,RC

    prod[0:127] <- (RA) * (RB)
    sum[0:127] <- prod + EXTS(RC)
    RT <- sum[0:63]

Special Registers Altered:

    None

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