[libre-riscv-dev] daily kan-ban update 25may2020

Cole Poirier colepoirier at gmail.com
Mon May 25 23:11:16 BST 2020

On May 25 2020, at 2:35 pm, Luke Kenneth Casson Leighton <lkcl at lkcl.net> wrote:
> in your wiki home page you will find a link to bugs assigned to you.  the
> default action is basically "monitor and do that list".

Thanks that makes it easy. I saw you assigned me 'Bug 337 - Convention
for register outputs in *OutputData structures is to use "Data"', and
looked at your comment. Is this simply reorg or is there something
additional I should be aware of?
> one to add:
> if you can also find the "interfaces" issue, and assign it to
> yourself, you
> will see a list of interfaces in the last comment, including "serialized
> irq" which you shouls find somewhere from raptor engineering.
> can you track the source code down, add them to the wiki  under the right
> subdurectory (shakti mclass) and also crossreference them in the bugtracker?

Are you referring to "Bug 304 - Define minimum viable interface set for
180nm ASIC", comment #6?
Luke Kenneth Casson Leighton 2020-05-20 23:14:26 BST

conversation notes from Tim (Raptor Engineering)


* 2x SPI master
* 4x I2C master
* 2x UART
* 4x LPC master
* EINT* Serialsed IRQ (LPC, from PCIe) - 15 or so IRQs, these are
PC>PCIe>OpenPower mappings

Quad SPI raptorengineering
LPC bridge github raptorengineering

I searched for "raptor serialized irq, and only found references to
raptors lpc-spi-bridge-fpga gitlab repo. Is this what we need
An in terms of adding the source code to the wiki, do you want me to
just copy and paste the 1000+ line verilog file or files to the
soc/libreriscv/shakti/m_class directory? Or do you want me to do
something similar to what you did for sdram.mdwn in the same directory?


* <https://bitbucket.org/casl/c-class/src/3fba75dfbd0c64815eb8ec6dc965666812c44bae/src/peripherals/sdram/?at=master>
* <https://opencores.org/projects/sdr_ctrl>


More information about the libre-riscv-dev mailing list