[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=305

--- Comment #58 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
left some TODOs in the code this morning, UK time:

@@ -41,6 +41,12 @@ class LogicalMainStage(PipeModBase):
             # TODO with m.Case(InternalOp.OP_POPCNT):
             ###### parity #######
             # TODO with m.Case(InternalOp.OP_PRTY):
+            ###### cmpb #######
+            # TODO with m.Case(InternalOp.OP_CMPB):
+            ###### cntlz #######
+            # TODO with m.Case(InternalOp.OP_CNTZ):
+            ###### bpermd #######
+            # TODO with m.Case(InternalOp.OP_BPERM): - not in microwatt

and cmp because it is so similar to ADD should go in ALU

  37         with m.Switch(self.i.ctx.op.insn_type):
  38             #### CMP, CMPL ####
  39             # TODO with m.Case(InternalOp.OP_CMP):

i've made the corresponding changes to power_enum Function (and to
the CSV files) already.

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