[libre-riscv-dev] daily kan-ban update 23may2020

[Cole Poirier]

On May 23 2020, at 1:59 pm, Luke Kenneth Casson Leighton <lkcl at lkcl.net> wrote:
> soc.fu they are now common base classes.  the code is exactly the
> same, it
> is just split.

I tried fixing this the naive way, by just substituting CommonInput
stageStage for LogicalInputStage but this results in the following error:

```
File "test_pipe_caller.py", line 193, in run_all
  m.submodules.alu = alu = LogicalBasePipe(pspec)
File "/home/colepoirier/src/soc/src/soc/fu/logical/pipeline.py", line
18, in __init__
  self.pipe1 = LogicalStages(pspec)
File "/home/colepoirier/src/nmutil/src/nmutil/dynamicpipe.py", line 37,
in __call__
 return super().__call__(*args, **kw)
File "/home/colepoirier/src/nmutil/src/nmutil/pipemodbase.py", line 34,
in __init__
  self.chain = self.get_chain()
File "/home/colepoirier/src/soc/src/soc/fu/logical/pipeline.py", line 9,
in get_chain
  inp = CommonInputStage(self.pspec)
TypeError: __init__() missing 1 required positional argument: 'modname'
```

Do I have to add something from fu/logical/logical_input_record.py, or
add something else in order to use CommonInputStage properly?


> one weirdness, if you put a print statement on a and b, a is a signal, but
> b ends up as an actual integer.

Are you referring to a and b of the CommonStage's or of another piece of code?

Cole