[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=325

--- Comment #3 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
section 7.5.9 covers TRAP, and shows that yes:

* SRR0 is set to "PC following trap"
* SRR1 contains the *old* MSR (sorry, not the new MSR)
* MSR is updated to meet the conditions of the trap

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