[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=325

Jacob Lifshay <programmerjake at gmail.com> changed:

           What    |Removed                     |Added
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                 CC|                            |programmerjake at gmail.com

--- Comment #4 from Jacob Lifshay <programmerjake at gmail.com> ---
I think this should also cover interrupts.

I would suggest having the execution unit be a FSM since traps/interrupts are
rare, so the FSM is not activated unless a trap/interrupt is taken. When we
receive an external interrupt, we could switch the decoder to insert a special
trap instruction instead of decoding normally.

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