[libre-riscv-dev] [Bug 317] New: multi-bit dependency tracking of split (ganged) regfile ports

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=317

            Bug ID: 317
           Summary: multi-bit dependency tracking of split (ganged)
                    regfile ports
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: PC
                OS: Mac OS
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Source Code
          Assignee: lkcl at lkcl.net
          Reporter: lkcl at lkcl.net
                CC: libre-riscv-dev at lists.libre-riscv.org
   NLnet milestone: ---

see https://bugs.libre-soc.org/show_bug.cgi?id=314#c14

this is a general technique which can be implemented on the INT and FP
regfiles as well as the Condition Registers and sub-fields of other SPRs
to provide W & R hazard protection against *portions* of a regfile.

it critically requires as a direct knock-on consequence that the protected
portion have its own read and write enable line.

thus the regfile may instead of being considered e.g. "64-bit wide" may
instead be considered 8x 8-bit wide, where 64-bit operations must request
*eight* simultaneous read/write-enable lines.

it's sufficiently comprehensive that we need to leave this off the TODO list
for now.

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