[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=305

--- Comment #77 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Michael Nolan from comment #76)

> Reported and the pseudocode has been fixed

great.  ran test_prty and it worked great.  hmm at some point we could do with
an option to run tests against qemu ppc[32/64][le/be]

next on the planning / TODO list, michael:

* OP_B* plus OP_TRAP, OP_RFID (anything that sets the PC by setting NIA)
* condition register stuff: OP_MFCR, OP_CROP, OP_MTCRF
* SPR stuff: OP_MTSPR and OP_MFSPR

probably good idea to raise separate bugreports for these.  i have no idea
where OP_ISEL or OP_MTMSRD would fit :)

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