[libre-riscv-dev] [Bug 348] POWER9 SPR pipeline needed

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=348

Jacob Lifshay <programmerjake at gmail.com> changed:

           What    |Removed                     |Added
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                 CC|                            |programmerjake at gmail.com

--- Comment #3 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #1)
>     if decode_spr_num(e_in.insn) = SPR_XER then
> 	-- bits 0:31 and 35:43 are treated as reserved and return 0s
>         -- when read using mfxer

from what I recall, at least some of the reserved XER bits are software
writable and need to be implemented.

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