[libre-riscv-dev] [Bug 335] Formal Correctness Proof for Branch pipeline

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Sun May 24 19:33:28 BST 2020


--- Comment #9 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
hm i feel the need to assert that when the cases are not being enabled,
the registers not in use (not changed) should be Asserted 0
(self.o.{something}.ok == 0)

this because if they are not zero they will cause a request for a
register port write at the MultiCompUnit, which, because their data
(self.o.{something}.data) was not initialised, would cause regfile

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