[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=305

--- Comment #54 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
oops soc.shift_rotate.input_stage missing.  remember use "git status" to check
:)

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