[libre-riscv-dev] Pinout, interfaces, Rudi, and Raptor
staf at fibraservi.eu
Sat May 9 10:12:40 BST 2020
Yehowshua schreef op vr 08-05-2020 om 10:20 [-0400]:
> Hello Luke, So I see we have some pinout sdefine here.
> https://libre-soc.org/shakti/m_class/pinouts/ <https://libre-soc.org/shakti/m_class/pinouts/>
> My suggestion is to drop the pinmux for now. We should probably update that page(or create a similar page) to reflect what we’re targeting for October.
> IIRC, we’re targeting QFP. I don’t see the dimensions or form factor we’re targeting listed there however. We should talk about that.
> Also, talked with Tim and SDR could work for the first SBC. LiteX also supports SDR which is good for us as it doesn’t require a PHY like DDR making it simpler.
You refer to a first SBC preferably low-cost. The October prototype tape-out will not be cost-effective for that. It is a multi-project wafer. You can order extra wafers but it does mean that the cost of that wafer is divided over much less devices; meaning the cost will be around $32 per chip and some of them will not be functional; in microelectrics you never have 100% yield. Also I think there is limit on only be able to get at most 1000 chips this way.
If you want lower cost per unit you need to go for a full mask with a so-called engineering lot of 12 wafers. This will have a high startup cost. A first crude estimation is between $70000 and $75000. This give a few thousand of chips; exact number depends on the size of the chip. An extra engineering lot of 12 wafers will be around $18000.
For this it means you will need to a new tape-out so you can add extra peripherals that were not on the prototype tape-out.
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