[libre-riscv-dev] [Bug 316] bperm TODO

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=316

--- Comment #90 from Cole Poirier <colepoirier at gmail.com> ---
(In reply to Michael Nolan from comment #89)
> (In reply to Cole Poirier from comment #88)
> > (In reply to Luke Kenneth Casson Leighton from comment #87)
> > > (In reply to Cole Poirier from comment #86)
> > > > Is there a way to access the values of the Signals instead of just their
> > > > type and name? It would be really useful if I could print the values of
> > > > signals while trying to get the test to pass.
> > > 
> > > x = yield val
> > > 
> > > then print (x)
> > 
> > I have tried doing the following:
> > ```
> > def elaborate(self, platform):
> >     m = Module()
> >     width = yield self.width
> >     rs = yield self.rs
> >     ra = yield self.ra
> >     rb = yield self.rb
> >     print("width: ", width, "rs: ", rs, "rb: ", rb, "ra: ", ra)
> > ```
> > 
> > Which unfortunately does not print the values, but gives me the following
> > error:
> > ```
> > File "/home/colepoirier/src/nmigen/nmigen/hdl/ir.py", line 50, in get
> >     raise AttributeError("Object {!r} cannot be elaborated".format(obj))
> > AttributeError: Object <generator object Bpermd.elaborate at 0x7f1f4ca00750>
> > cannot be elaborated
> > ```
> > 
> > What am I doing wrong?
> 
> Sorry, the x = yield sig only works inside the simulator. There's not a way
> to print the value of a signal from inside the module itself
> 
> This should make sense, the module is *building* a circuit, it has no idea
> what the values of any of the parts of the circuit are while it's being
> built.

I see. Thank you, that does indeed make sense. I've been working on this for a
few hours and am struggling. I'm going to try writing this in regular python
code so I can debug print the values, and properly understand how endian-ness
affects the code.

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